A dynamic random access memory (DRAM) memory cell typically includes a storage capacitor and an access transistor coupled to the storage capacitor. The physical data state, a logic “1” or “0,” stored in the memory cell corresponds to the electric charge held within the capacitor of the cell. The access transistor functions as a switch through which charge is transferred between the memory cell and the corresponding local bit line to which the memory cell is connected during a read, write or refresh operation. The operation of DRAM memory is well known in the art.
A DRAM macro, including embedded DRAM (eDRAM), typically includes, not only DRAM memory cells but also a plurality of storage, sensing and data path circuits, on-pitch column circuitry, on-pitch row circuitry, control circuitry, data-in inputs, data-out outputs, address inputs, and control inputs. Each storage, sensing and data path circuit typically comprises at least one sense amplifier.
A sense amplifier having a lower transistor count was developed that would support fewer corresponding memory cells without impacting area efficiency of the DRAM macro (See, e.g., J. Barth et al., “A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 1, January 2008). Fewer cells lighten the bit line load and, hence, improve the time constant associated with reading the memory cells. This new and fast sense amplifier is known as a micro sense amplifier (μSA). Eight of these μSAs may be employed, for example, in one storage, sensing and data path circuit. During a read, write, or refresh cycle, only one μSA for each bit line group within each storage, sensing and data path circuit is active; that is, within each storage, sensing and data path circuit, only one μSA associated with each bit line group is involved in detecting, writing or refreshing a stored data state within a memory cell. The remaining μSAs for each bit line group are inactive; that is, they are not involved in detecting, writing or refreshing a stored data state within a memory cell. In this arrangement, there are typically a plurality of memory cells coupled to a given local bit line (LBL), which are, in turn, coupled to one μSA.
The conventional μSA is sensitive to noise and process variations. These effects not only degrade noise immunity of the μSA, but also may, in some cases, lead to erroneous read operations. Typically, the noise sensitivity of the μSA limits the number of cells that can be associated with one μSA and still maintain adequate signal margins. Consequently, the area efficiency of such a DRAM macro is limited because more of the fractional area must be devoted to peripheral circuits (e.g., μSA) and less to memory cells, which is undesirable.